The present invention relates to optoelectronic devices and, in particular, to the integration of photodetectors and transistors integrated on a substrate.
The speed at which optical networking devices operate can be increased by using integrated circuits that provide both optical and electronic functions. Optoelectronic integrated circuits (OEICs), in particular, combine photodetectors, which convert optical to electronic signals, with transistors, used to electronically amplifying the detector signals, on a single substrate. Integrating these components on a substrate circuit has the potential to greatly increase the speed (in excess of 40 Gb/s) and to decrease the cost of high-speed networking components through the development of compact optical circuits for optical networking.
One technique for developing components that allow for OEICs is the integration of p-i-n photodiodes (PIN-PDs) with single heterojunction bipolar transistors (single HBT, or SHBT), referred to herein as xe2x80x9cPIN/HBT integration.xe2x80x9d HBTs have proven large-scale integration capability and also have the potential for use as optical transceiver modules with signal processing front ends such as multiplexer, de-multiplexer, and clock-and-data-recovery circuits. PIN/HBT integration is based on structural similarities of certain PIN-PDs and SHBTs that allow these components to be fabricated from a single stack of semiconductor layers. In particular, it is known that a stack of semiconductor layers can be used to form both the base and collector of a SHBT and a PIN-PD. For example, one prior art circuit is based on a separate PIN-PD structure grown on the bottom of a HBT structure which includes a SHBT and a double HBT (DHBT) on top of the PIN-PD structure. While this allows for integration of photodiodes and transistors, this approach suffers from several drawbacks that limit the application of such devices to high-speed applications, such as the inability to produce photodiodes with high responsivity to light and transistors that operate at high speed when the devices are formed from the same semiconductor layers.
Other techniques have also been developed or proposed based on the etching and regrowth of structures. One prior art device uses an epitaxial PIN-PD on top of a SHBT that is located on a partially recessed indium phosphate (InP) substrate, and another has a PIN-PD that is grown on a recessed InP substrate with subsequent HBT layers grown after the removal of layers of the PIN-PD outside of the recess, for circuit planarization purposes. While these structures achieve monolithic integration of a high responsivity PIN-PD with a high-speed SHBT, manufacturability is a major concern since the regrowth technique is currently incompatible with common-practice fabrication processes, and hence is not economical.
Another technique for developing components that are compatible with OEICs is the integration of PIN-PDs with high electron mobility transistors (HEMTs) or Pseudomorphic HEMTs. One limitation of this approach is that HMET manufacturing techniques are appropriate for circuits having only a small amount of circuit integration. Another limitation of this approach is that HEMTs have limited speeds that result from noise levels that increase for bit rates greater than 2 Gb/s.
It is also desirable to increase the speed and sensitivity of the PDs in OEICs. The sensitivity of photon detection can be increased by increasing the absorption layer thickness of the PD. High-speed responsivity is limited by the transit time of the photo-generated current due to the relatively long interaction length. Many solutions have been proposed to increase the photoresponsivity while maintaining low photocurrent transit time and reasonable RC time constant. One proposed solution is to provide a waveguide photodetector. However, due to the difficulty of these light coupling schemes and the inability to produce them with monolithic integration, only discrete devices are available to date. For monolithic integration of OEICs, surface-normal photodetectors appear to be the only viable solution in the prior art. This configuration greatly limits the ability to couple light into the photodetector.
In summary, prior art techniques for integrating components in an OEIC are either too slow for high-speed use, are not amenable for use with high levels of integration, or use manufacturing techniques that are expensive or are not standard semiconductor manufacturing techniques.
What is needed is a semiconductor structure that allows for the fabrication of high-speed transistors and high responsivity photodiodes using techniques that are both economical and compatible with common fabrication techniques. Such a structure should be based on semiconductor layers and fabrication techniques that are commonly used, allowing for the production of advanced integrated circuits with a minimal amount of extra effort and expense. The resulting circuit should be based on the monolithic integration of both high-sensitivity photo-detector and high-speed, high linearity HBTs that can be used for circuits operating at 40 Gb/s or greater.
The present invention solves the above-identified problems of known OEICs by providing photodiode and transistor structures that can be fabricated using prior art semiconductor fabrication techniques from a single stack of semiconductor layers on a substrate, resulting in high-speed, linear HBTs and high-sensitivity photodetectors in a single integrated circuit.
It is one aspect of the present invention to provide a structure for forming integrated HBTs and PDs using a common stack of semiconductor layers for operation of OEICs at speeds of 40 Gb/s or greater.
It is another aspect of the present invention to provide a structure for forming integrated HBTs and PDs using a common stack of semiconductor layers. It is another aspect of the present invention that the structure allows for the integration of all InP-based and GaAs-based SHBTs and DHBT.
It is yet another aspect of the present invention to provide a structure for forming integrated HBTs and PDs that facilitate wet-etching HBT fabrication processes using current selective etching techniques, and possibly combined dry-etching such as reactive-ion-etching (RIE) or inductively-coupled-plasma (ICP) etching techniques in both GaAs- and InP-based HBTs.
It is an aspect of the present invention to provide a structure for forming integrated HBTs and PDs that can be manufactured on lattice-matched to InP substrates or on strained layers compatible with InP-based and GaAs-based semiconductors.
It is one aspect of the present invention to provide integrated optoelectronic components formed from a plurality of adjacent layers including sequential first, second and third layers on a substrate. The components include at least one single-heterojunction bipolar transistor formed from an emitter layer and from the first, second and third layers, where the first layer forms a transistor base, the second layer forms a transistor collector, and the third layer forms a transistor subcollector. The components also include at least one p-i-n-i-p photodiode formed from the first, second and third layers, where the first layer forms a photodiode p-type layer, where the second layer forms a photodiode i-type layer, and the third layer forms a photodiode n-type layer.
It is one aspect of the present invention to provide integrated optoelectronic components formed from a plurality of adjacent layers including sequential first, second and third layers on a substrate. The components include at least one p-i-n-i-p photodiode formed from the plurality of layers and at least one single-heterojunction bipolar transistor formed from the plurality of layers, and includes adjacent p-type, i-type, and n-type layers of said at least one p-i-n-i-p photodiode.
It is another aspect of the present invention to provide integrated optoelectronic circuit components formed from a plurality of layers on a substrate. The components include a first group of the plurality of layers forming a reflector, a second group of the plurality of layers on said first group and forming at least one bipolar heterojunction transistor, and a third group of the plurality of layers on said first group and forming at least one photodiode. The reflector is positioned to double-pass light through said at least one photodiode by reflecting light transmitted through the at least one photodiode back through said photodiode.
A further understanding of the invention can be had from the detailed discussion of the specific embodiment below. For purposes of clarity, this discussion refers to devices, methods, and concepts in terms of specific examples. However, the method of the present invention may be used to connect a wide variety of types of devices. It is therefore intended that the invention not be limited by the discussion of specific embodiments.